The present invention relates generally to Electrically Erasable Programmable Read Only Memory (EEPROM), and more particularly to an EEPROM array having a split common source for reducing Vpp loading during programming memory bit cells of the EEPROM array.
EEPROM is a class of nonvolatile semiconductor memory in which information may be electronically programmed into and erased from each memory element or bit cell. Each bit cell of the EEPROM comprises two metal oxide semiconductor field effect transistors (MOSFET), one of the MOSFETs has two gates and is used to store the bit information, and the other MOSFET is used in the selection of the bit cell. Illustrated in FIG. 1a is a cross-section elevation view of a semiconductor integrated circuit bit cell 200 comprising a storage MOSFET 202 having two gates, a memory cell gate 102 and a floating gate 104, one above the other. A source well 108 and common drain/source well 118 make up the remaining elements of the MOSFET 202. A row select MOSFET 204 comprises the common drain/source well 118, a row select gate 112 and a drain well 110. FIG. 1b is a schematic diagram of the bit cell 200 illustrated in FIG. 1a. The gates 102, 104 and 112 may be poly-silicon or other conductive material. The lower gate 104 is surrounded by an oxide 114 and is thereby insulated from and unconnected to any voltage or other element of the bit cell MOSFET 200. The double gate MOSFET 202 is called a xe2x80x9cfloating-gate tunneling-oxidexe2x80x9d or FLOTOX EEPROM.
FIG. 2 is a schematic diagram illustrating a portion of a typical prior art EEPROM comprising a plurality of bit cells 200 arranged in a matrix array. The memory element or bit cell generally indicated by the numeral 200 may be read from, written to, erased, or put in standby according to Table I below:
VDD may be generally from about 5.0 volts but may be in the one volt range depending upon the operation of the EEPROM. Vpp may be generally from about 18-23 volts. Vpp+ may be generally from about 21-25 volts.
To erase or write to a bit cell 200, the row select transistor must have a relatively high potential pulse of Vpp+. The Vpp+ pulse, and any other high potential voltages required, may be internally generated in the EEPROM integrated circuit by a charge pump, with the only other external voltage required being VDD. Vpp may be derived form Vpp+ and is therefore part of the load on the charge pump. The only difference between an Erase and a Write is the direction of the applied field potential relative to the floating gate 104. The high voltage Vpp+ pulse may be from about 0.1 to 10 milliseconds.
For example, when Vpp is applied to the memory cell gate 222b and 0 volt is applied to bit line drain (column) 230c, electrons tunnel from the substrate 106 through the dielectric oxide 114 to the floating gate 104 until the floating gate 104 is charged. The cell 200 is now at an Erase state of logic 1. When 0 volt is applied to the memory cell gate 222b and Vpp is applied to bit line drain (column) 230c, electrons tunnel from the floating gate 104 through the dielectric oxide 114 to the substrate 106 until the floating gate 104 is discharged. The cell 200 is now at a Write state of logic 0. This sequence of transferring charge onto the floating gate 104 (Erase) and the removal of the charge therefrom (Write) is one Erase/Write cycle, or xe2x80x9cE/W cycle.xe2x80x9d Incidental to writing the bit cell 200, the source 108 is pulled high (to approximately 10 volts).
For reliable operation of an Erase/Write cycle to a bit cell(s), the Vpp+ pulse must charge up to its maximum value quickly. A finite amount of time at finite voltages are required to achieve xe2x80x9coptimalxe2x80x9d Erase and Write thresholds. If the Vpp+ pulse is too short and the voltage applied to the bit cell too low, the bit cell(s) 200 will not be programmed to the proper threshold, thereby degrading the reliability and robustness of data stored in the EEPROM.
The on-chip charge pump has limited charging capabilities to generate the Vpp+ pulse during a write operation. A significant amount of capacitance and cell leakage currents load the output of the charge pump. The capacitance comprises the parallel combination of the parasitic capacitance Cgs and Cds present at each of the MOSFETs 202 and 204 in the bit cell 200. The cell leakage is from imperfect insulation properties of materials used in fabrication of the EEPROM and elevated operating temperatures. Also, the array source 108 has a large amount of capacitance to the substrate which must be pulled high by the charge pump.
As EEPROM array bit densities increase, the on-chip charge pump of such a chip begins having trouble pulling the Vpp+ line to a reliable programming voltage during a write cycle. Attempts have been made to increase the drive (charging) capabilities of the charge pump so as to obtain the desired programming response time with a larger (higher capacitive) load. Also, attempts at reducing the Vpp+ leakage have been made to further reduce the loading of the charge pump during a write cycle. High drive capacity (stronger) charge pumps require more integrated circuit die area and/or more operating current. Reducing the bit cell device leakage currents would also require larger device structures with a resultant increase in die size. As higher bit capacity EEPROMs are being fabricated using smaller transistor structures, these attempts at improving cell writing reliability are counter productive or impossible to achieve.
The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing an EEPROM bit cell array structure having the array source lines divided into two or more segments for reducing the bit cell loading of the Vpp+ pulse during a Write operation. These segments may be as small as only the bit cells being written to (one byte, word, etc.). The charge pump need only be connected to the bit cell segment being programmed. Segmentation of the common source reduces the amount of parasitic capacitance connected in the EEPROM array during a Write operation. Reducing the number of bit cells connected during a Write operation may further reduce the amount of leakage current contributions to a bit cell(s) in a segment(s). A further reduction in charge pump drive capacitance is feasible since a reduction of loading can be achieved through appropriate segmentation of the bit cell array devices.
Accordingly, an exemplary embodiment of the invention is directed to an electrically erasable and programmable read only memory (EEPROM), comprising a plurality of memory bit cells wherein said plurality of memory bit cells are divided into at least two groups of bit cells, each of said at least two groups of bits cells have a common circuit connection separate from the other ones of said at least two groups of bits cells, and at least two selection circuits, each of said at least two selection circuits connected to the common circuit connection of a respective one of said at least two groups of bit cells, wherein said at least two selection circuits are adapted for selecting one of said at least two groups of bits cells when performing an operation on at least one bit cell thereof.
In accordance with an exemplary embodiment of the present invention, the bit cell array of an EEPROM has connections to the sources of the transistor devices comprising the bit cells segmented into two or more separate circuits. This segmentation reduces charge pump loading during a write operation to a selected bit cell(s) by reducing the number of transistor devices that contribute parasitic capacitance and leakage currents to the load that the charge pump must drive during the write operation.
The common circuit connection may be a common source connection. The each of the at least two selection circuits may comprise at least one selection transistor connected to a respective one of the common source connections of the at least two groups of bit cells. The plurality of bit cells may comprise a storage transistor and a select transistor. The storage transistor may comprise a floating gate and a cell gate, the floating gate being located between the cell gate, a source and a common drain/source. The select transistor comprises a select gate, a drain and the common drain/source. The source of the storage transistor is connected to the common source connection of a one of the at least two groups of bit cells. The operation is selected from the group consisting of read, write, erase and standby.
A programming pulse may perform the operation on the at least one bit cell. The programming pulse may have a time duration of from about 0.1 to 10 milliseconds. The programming pulse may have an amplitude of from about 21 to 25 volts. The programming pulse may also have an amplitude of from about 18 to 23 volts.
An electron charge is stored on the floating gate of the storage transistor by connecting the source of said storage transistor and the drain of the select transistor to a power supply common voltage, and applying a programming pulse to the cell gate and the row select gate. The electron charge on the floating gate of the storage transistor is discharged by connecting the cell gate to a power supply common voltage, floating the source of the storage transistor and applying a programming pulse to the row select gate and the drain of said select transistor.
In addition, the present invention is also directed to a method of operation for an electrically erasable and programmable read only memory (EEPROM), said method comprising the steps of dividing a plurality of memory bit cells into at least two groups of bit cells, each of said at least two groups of bits cells having a common circuit connection separate from the other ones of said at least two groups of bits cells; and connecting each of at least two selection circuits to the common circuit connections of a respective one of said at least two groups of bit cells, wherein said at least two selection circuits are adapted for selecting one of said at least two groups of bits cells when performing an operation on at least one bit cell thereof.
The step of storing an electron charge on the floating gate of the storage transistor comprises the steps of applying a power supply common voltage to the source of the storage transistor and the drain of the select transistor, and applying a programming pulse to the cell gate and the row select gate. The step of discharging an electron charge on the floating gate of the storage transistor comprises the steps of applying a power supply common voltage to the cell gate, floating the source of said storage transistor and applying a programming pulse to the row select gate and the drain of said select transistor.
The step of performing the operation on the at least one bit cell may be done with a primary programming pulse (designated herein as Vpp+). The primary programming pulse may have a time duration of from about 0.1 to 10 milliseconds, and an amplitude of from about 21 to 25 volts. Other high potential pulse levels required will be less than Vpp+ but higher than VDD (normal operation drain voltage).
A technical advantage of the present invention is reduced loading of a charge pump resulting in faster rise times for write pulses in EEPROM. Another technical advantage is improved reliability of write operations in an EEPROM. Still another technical advantage is scalable bit cell arrays being driven by a low power charge pump write circuit. Another advantage is faster write times in high capacity EEPROM.
Features and advantages of the invention will be apparent from the following description of the embodiments, given for the purpose of disclosure and taken in conjunction with the accompanying drawings.